Title

PMOS breakdown effects on digital circuits - Modeling and analysis

Authors

Authors

W. D. Kuang; L. Z. Cao; C. Yu;J. S. Yuan

Comments

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Abbreviated Journal Title

Microelectron. Reliab.

Keywords

Engineering, Electrical & Electronic; Nanoscience & Nanotechnology; Physics, Applied

Abstract

The degradations in the pMOS device due to gate oxide breakdown introduced by voltage stress were investigated experimentally. The stress-induced shifts in gate leakage and I-V characteristics were presented. A combined Verilog-A and sub-circuit model was first time introduced and employed to simulate the pMOS breakdown behaviors. The Verilog-A model can accurately simulate the power law characteristics of breakdown gate leakage Current with a fractional coefficient. With the developed model, the simulated results and the measurements have good agreements. The traditional logic circuits, such as the inverter and the latch, have been investigated through Cadence simulations with the improved models, The latch suffers front the gate oxide breakdown significantly. The NULL Convention Logic (NCL) circuit has also been examined and analyzed systematically. The results showed substitute degradations due to the pMOS gate oxide breakdown. (C) 2008 Elsevier Ltd. All rights reserved.

Journal Title

Microelectronics Reliability

Volume

48

Issue/Number

8-9

Publication Date

1-1-2008

Document Type

Article; Proceedings Paper

Language

English

First Page

1597

Last Page

1600

WOS Identifier

WOS:000260347000099

ISSN

0026-2714

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