Title

A new model for four-terminal junction field-effect transistors

Authors

Authors

H. Ding; J. J. Liou; K. Green;C. R. Cirba

Comments

Authors: contact us about adding a copy of your work at STARS@ucf.edu

Abbreviated Journal Title

Solid-State Electron.

Keywords

field effect transistors; analog circuit; compact modeling; FET; Engineering, Electrical & Electronic; Physics, Applied; Physics, ; Condensed Matter

Abstract

This paper presents a compact and semi-empirical model for a four-terminal (independent top and bottom gates) junction field-effect transistor (JFET). The model describes the steady-state characteristics for all bias conditions with a unified equation. Moreover, the model provides a high degree of accuracy and continuity for the different operation regions, a critical factor for robust analog circuit simulations. Capacitance modeling is also included to describe the JFET small-signal behavior. The model has been implemented in Cadence framework via Verilog-A and compared with data measured from JFETs used at Texas Instruments. (c) 2006 Elsevier Ltd. All rights reserved.

Journal Title

Solid-State Electronics

Volume

50

Issue/Number

3

Publication Date

1-1-2006

Document Type

Article

Language

English

First Page

422

Last Page

428

WOS Identifier

WOS:000237616500020

ISSN

0038-1101

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