A high throughput 3D-bus interconnect for network processors

    Authors

    T. Kocak;J. Engel

    Comments

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    Abbreviated Journal Title

    Microprocess. Microsyst.

    Keywords

    network processors; memory management; line cards; interconnect systems; k-ary n-cube networks; Computer Science, Hardware & Architecture; Computer Science, Theory &; Methods; Engineering, Electrical & Electronic

    Abstract

    Deep layer processing and increasing line rates present a memory challenge to processor-memory communications located on network line cards. In this paper, we introduce a packet-based, off-chip interconnect to increase the throughput of memory system currently used on line cards. The 3D-bus architecture allows multiple packet processing elements on a line card to access multiple memory modules. Our network-on-board includes a routing protocol as well as a node switching mechanism to minimize packet congestion and packet loss. The main advantage of the proposed architecture is to increase the network processor off-chip memory bandwidth while diminishing the latency otherwise caused by the single bus competition. Performance results show that our interconnect significantly outperforms its competitors, such as shared-bus, PCI Express, infiniband and HyperTransport, reaching peak throughput beyond 400 Gbps. Moreover, it provides other high performance qualities including low latency, off-chip scalability, low transmission failure-rate and high memory bandwidth. (c) 2005 Elsevier B.V. All rights reserved.

    Journal Title

    Microprocessors and Microsystems

    Volume

    30

    Issue/Number

    1

    Publication Date

    1-1-2006

    Document Type

    Article

    Language

    English

    First Page

    15

    Last Page

    25

    WOS Identifier

    WOS:000235353800002

    ISSN

    0141-9331

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