Characterization and modeling of flicker noise in junction field-effect transistor with source and drain trench isolation

    Authors

    Y. Fu; H. Wong;J. J. Liou

    Comments

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    Abbreviated Journal Title

    Microelectron. Reliab.

    Keywords

    LOW-FREQUENCY NOISE; GENERATION; INTERFACE; DEVICES; OXIDE; Engineering, Electrical & Electronic; Nanoscience & Nanotechnology; Physics, Applied

    Abstract

    The flicker or low-frequency noise behaviors of the junction field-effect transistor (JFET) with source and drain shallow trench isolation (STI) regions for planner technology are studied in detail. High noise level is found in the devices with the source and drain isolation and the normalized drain flicker noise is found to be gate bias dependent. The excess noise is identified as the surface noise generated at the oxide/Si interface in the isolation regions and a model is developed to explain the bias dependencies of the noise level and frequency index of the noise spectra. Although a larger low-frequency noise was found in the STI-JFET when compared with the conventional bulk type JFET, it is still an attractive structure for integrating into CMOS technology for low-noise analog applications. The noise level can be further minimized by keeping STI region small and using a better oxidation technique for the STI passivation. (c) 2006 Elsevier Ltd. All rights reserved.

    Journal Title

    Microelectronics Reliability

    Volume

    47

    Issue/Number

    1

    Publication Date

    1-1-2007

    Document Type

    Article

    Language

    English

    First Page

    46

    Last Page

    50

    WOS Identifier

    WOS:000244006500007

    ISSN

    0026-2714

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