Title

Self-timed architecture for masked successive approximation analog-to-digital conversion

Authors

Authors

T. Kocak; G. R. Harris;R. F. Demara

Comments

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Abbreviated Journal Title

J. Circuits Syst. Comput.

Keywords

asynchronous digital systems; self-timed designs; analog-to-digital; conversion; null convention logic; successive approximation; CIRCUITS; Computer Science, Hardware & Architecture; Engineering, Electrical &; Electronic

Abstract

In this paper, a novel architecture for self-timed analog-to-digital conversion is presented and designed using the NULL Convention Logic (NCL) paradigm. This analog-to-digital converter (ADC) employs successive approximation and a one-hot encoded masking technique to digitize analog signals. The architecture scales readily to any given resolution by utilizing the one-hot encoded scheme to permit identical logical components for each bit of resolution. The four-bit configuration of the proposed design has been implemented and assessed via simulation in 0.18-mu m CMOS technology. Furthermore, the ADC may be interfaced with either synchronous or four-phase asynchronous digital systems.

Journal Title

Journal of Circuits Systems and Computers

Volume

16

Issue/Number

1

Publication Date

1-1-2007

Document Type

Article

Language

English

First Page

1

Last Page

14

WOS Identifier

WOS:000250863700001

ISSN

0218-1266

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