A review of core compact models for undoped double-gate SOI MOSFETs

    Authors

    A. Ortiz-Conde; F. J. Garcia-Sanchez; J. Muci; S. Malobabic;J. J. Liou

    Comments

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    Abbreviated Journal Title

    IEEE Trans. Electron Devices

    Keywords

    asymmetric double-gate (DG) MOSFET; drain-current model; intrinsic; channel; MOS compact modeling; multigate MOSFET; silicon-on-insulator; (SOI) MOSFET; symmetric DG MOSFET; undoped body MOS; THIN-FILM SOI; DRAIN-CURRENT; ANALYTIC SOLUTION; DG MOSFETS; SILICON; FUTURE; CHARGE; TECHNOLOGY; Engineering, Electrical & Electronic; Physics, Applied

    Abstract

    In this paper, we review the compact-modeling framework for undoped double-gate (DG) silicon-on-insulator (SOI) MOSFETs. The use of multiple gates has emerged as a new technology to possibly replace the conventional planar MOSFET when its feature size is scaled to the sub-50-nm regime. MOSFET technology has been the choice for mainstream digital circuits for very large scale integration as well as for other high-frequency applications in the low-gigahertz range. But the continuing scaling of MOSFET presents many challenges, and multiple-gate, particularly DG, SOI devices seem to be attractive alternatives as they can effectively reduce the short-channel effects and yield higher current drive. Core compact models, including the analysis for surface potential and drain-current, for both the symmetric and asymmetric DG SOI MOSFETs, are discussed and compared. Numerical simulations are also included in order to assess the validity of the models reviewed.

    Journal Title

    Ieee Transactions on Electron Devices

    Volume

    54

    Issue/Number

    1

    Publication Date

    1-1-2007

    Document Type

    Review

    Language

    English

    First Page

    131

    Last Page

    140

    WOS Identifier

    WOS:000243280500018

    ISSN

    0018-9383

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