Intrinsic evolvable hardware platform for digital circuit design and repair using genetic algorithms

    Authors

    R. S. Oreifej;R. F. DeMara

    Comments

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    Abbreviated Journal Title

    Appl. Soft. Comput.

    Keywords

    Evolvable hardware; Intrinsic fitness evaluation; Direct bitstream; manipulation; Partial crossover operators; Autonomous fault recovery; RELIABILITY; FPGA; Computer Science, Artificial Intelligence; Computer Science, ; Interdisciplinary Applications

    Abstract

    A hardware/software platform for intrinsic evolvable hardware is designed and evaluated for digital circuit design and repair on Xilinx Field Programmable Gate Arrays (FPGAs). Dynamic bitstream compilation for mutation and crossover operators is achieved by directly manipulating the bitstream using a layered framework. Experimental results on a case study have shown that benchmark circuit evolution from an unseeded initial population, as well as a complete recovery of a stuck-at fault is achievable using this platform. An average of 0.47 mu s is required to perform the genetic mutation, 4.2 mu s to perform the single point conventional crossover, 3.1 mu s to perform Partial Match Crossover (PMX) as well as Order Crossover (OX), 2.8 mu s to perform Cycle Crossover (CX), and 1.1 ms for one input pattern intrinsic evaluation. These represent a performance advantage of three orders of magnitude over the JBITS software framework and more than seven orders of magnitude over the Xilinx design tool driven flow for realizing intrinsic genetic operators on Xilinx Virtex Family devices. (C) 2012 Elsevier B. V. All rights reserved.

    Journal Title

    Applied Soft Computing

    Volume

    12

    Issue/Number

    8

    Publication Date

    1-1-2012

    Document Type

    Article

    Language

    English

    First Page

    2470

    Last Page

    2480

    WOS Identifier

    WOS:000305275800050

    ISSN

    1568-4946

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