Title

Scalable FPGA Refurbishment Using Netlist-Driven Evolutionary Algorithms

Authors

Authors

R. A. Ashraf;R. F. DeMara

Comments

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Abbreviated Journal Title

IEEE Trans. Comput.

Keywords

Evolvable hardware; SRAM-based FPGAs; scalability of genetic algorithms; hard/permanent fault refurbishment; self-healing; survivability; search; space pruning; selective mutation; EVOLVABLE HARDWARE; RELIABILITY-ANALYSIS; FAULT RECOVERY; RECONFIGURATION; CHALLENGES; COMPONENTS; LIFETIME; SYSTEMS; Computer Science, Hardware & Architecture; Engineering, Electrical &; Electronic

Abstract

In this work, Field-Programmable Gate Array (FPGA) reconfigurability is exploited to realize autonomous fault recovery in mission-critical applications at runtime. The proposed Netlist-Driven Evolutionary Refurbishment technique utilizes design-time information from the circuit netlist to constrain the search space of the algorithm by up to 98.1 percent in terms of the chromosome length representing reconfigurable logic elements. This facilitates refurbishment of relatively large-sized FPGA circuits as compared to previous works. Hence, the scalability issue associated with Evolvable Hardware-Based refurbishment is addressed and improved. Experiments are conducted with multiple circuits from the MCNC benchmark suite to validate the approach and assess its benefits and limitations. Successful refurbishment of the apex4 circuit having a total of 1,252 LUTs with 10 percent spares is achieved in as few as 633 generations on average when subjected to simulated randomly injected single stuck-at faults. Moreover, the use of design-time information about the circuit undergoing refurbishment is validated as means to increase the tractability of dynamic evolvable hardware techniques.

Journal Title

Ieee Transactions on Computers

Volume

62

Issue/Number

8

Publication Date

1-1-2013

Document Type

Article

Language

English

First Page

1526

Last Page

1541

WOS Identifier

WOS:000321221000005

ISSN

0018-9340

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