Design of Asynchronous Circuits for High Soft Error Tolerance in Deep Submicrometer CMOS Circuits

    Authors

    W. D. Kuang; P. Y. Zhao; J. S. Yuan;R. F. DeMara

    Comments

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    Abbreviated Journal Title

    IEEE Trans. Very Large Scale Integr.

    Keywords

    Asynchronous circuit; null convention logic (NCL); soft error; Computer Science, Hardware & Architecture; Engineering, Electrical &; Electronic

    Abstract

    As the devices are scaling down, the combinational logic will become susceptible to soft errors. The conventional soft error tolerant methods for soft errors on combinational logic do not provide enough high soft error tolerant capability with reasonably small performance penalty. This paper investigates the feasibility of designing quasi-delay insensitive (QDI) asynchronous circuits for high soft error tolerance. We analyze the behavior of null convention logic (NCL) circuits in the presence of particle strikes, and propose an asynchronous pipeline for soft-error correction and a novel technique to improve the robustness of threshold gates, which are basic components in NCL, against particle strikes by using Schmitt trigger circuit and resizing the feedback transistor. Experimental results show that the proposed threshold gates do not generate soft errors under the strike of a particle within a certain energy range if a proper transistor size is applied. The penalties, such as delay and power consumption, are also presented.

    Journal Title

    Ieee Transactions on Very Large Scale Integration (Vlsi) Systems

    Volume

    18

    Issue/Number

    3

    Publication Date

    1-1-2010

    Document Type

    Article

    Language

    English

    First Page

    410

    Last Page

    422

    WOS Identifier

    WOS:000274995400007

    ISSN

    1063-8210

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