Failure Analysis of Si Nanowire Field-Effect Transistors Subject to Electrostatic Discharge Stresses

    Authors

    W. Liu; J. J. Liou; Y. Jiang; N. Singh; G. Q. Lo; J. Chung;Y. H. Jeong

    Comments

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    Abbreviated Journal Title

    IEEE Electron Device Lett.

    Keywords

    Degradation; electrostatic discharge (ESD); failure analysis; gate oxide; breakdown; nanowire field-effect transistor (NW FET); GATE; PERFORMANCE; PROTECTION; DESIGN; Engineering, Electrical & Electronic

    Abstract

    The failure mechanisms of silicon nanowire field-effect transistors subject to electrostatic discharge (ESD) stresses are investigated using electrical characterization and microscopy analysis. Current-voltage measurements are carried out before and after the devices are stressed with ESD equivalent pulses generated from the transmission line pulsing (TLP) tester. Depending on the TLP stress level, either a soft or a hard failure can take place in the nanowire devices due to the nondestructive damage or destructive fusing of nanowires and the surrounding gate oxide.

    Journal Title

    Ieee Electron Device Letters

    Volume

    31

    Issue/Number

    9

    Publication Date

    1-1-2010

    Document Type

    Article

    Language

    English

    First Page

    915

    Last Page

    917

    WOS Identifier

    WOS:000283185500005

    ISSN

    0741-3106

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