Title

vfTLP-V-TH: A new method for quantifying the effectiveness of ESD protection for the CDM classification test

Authors

Authors

Y. Z. Zhou; D. Ellis; J. J. Hajjar; A. Olney;J. J. Liou

Comments

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Abbreviated Journal Title

Microelectron. Reliab.

Keywords

MOSFET DEGRADATION; OXIDE; Engineering, Electrical & Electronic; Nanoscience & Nanotechnology; Physics, Applied

Abstract

A new methodology for quantifying the effectiveness of CDM protection circuits and CDM robustness of I/O circuits is presented in this paper. This method, referred to as the vfTLP-V-TH, consists of applying vfTLP stresses to test structures composed of the ESD protection and the device or circuit to be protected: a MOS device or a MOS inverter. The protected structures are used as monitors and shifts in their characteristics, such as MOS threshold voltage V-TH and saturation current I-DD, are used to probe device failure criteria. (C) 2012 Elsevier Ltd. All rights reserved.

Journal Title

Microelectronics Reliability

Volume

53

Issue/Number

2

Publication Date

1-1-2013

Document Type

Article

Language

English

First Page

196

Last Page

204

WOS Identifier

WOS:000315614600004

ISSN

0026-2714

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