Analysis of Safe Operating Area of NLDMOS and PLDMOS Transistors Subject to Transient Stresses

    Authors

    S. Malobabic; J. A. Salcedo; J. J. Hajjar;J. J. Liou

    Comments

    Authors: contact us about adding a copy of your work at STARS@ucf.edu

    Abbreviated Journal Title

    IEEE Trans. Electron Devices

    Keywords

    Laterally diffused metal-oxide-semiconductor (LDMOS); transient safe; operating area (TSOA); transmission line pulsing (TLP); very fast; transmission line pulse (VFTLP); Engineering, Electrical & Electronic; Physics, Applied

    Abstract

    Transient safe operating area (TSOA) of n-type and p-type laterally diffused metal-oxide-semiconductor (LDMOS) subject to transient stresses is presented for electrostatic discharge applications. LDMOS devices connected in the gate-grounded and gate-biased configurations are stressed with 1-, 2-, 5-, 10-, and 100-ns duration transmission line pulses, and a methodology to develop an effective and accurate TSOA based on these measurements is discussed. Two-dimensional technology computer-aided design simulations are also used to discuss critical physical mechanisms governing the current conduction during the transients and the condition that finally leads to device failure beyond the TSOA.

    Journal Title

    Ieee Transactions on Electron Devices

    Volume

    57

    Issue/Number

    10

    Publication Date

    1-1-2010

    Document Type

    Article

    Language

    English

    First Page

    2655

    Last Page

    2663

    WOS Identifier

    WOS:000283346500039

    ISSN

    0018-9383

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