Title

Methodology for adapting on-chip interconnect architectures

Authors

Authors

S. Suboh; V. Narayana; M. Bakhouya; J. Gaber;T. El-Ghazawi

Comments

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Abbreviated Journal Title

IET Comput. Digit. Tech.

Keywords

computer architecture; network-on-chip; quality of service; adapting; onchip interconnect architecture methodology; Network-on-Chip; NoC; scalability problem; bus based system-on-chip; quality of service; network infrastructure; predictable electrical parameters; programmable; infrastructure; traffic pattern application; NETWORK; SYSTEMS; Computer Science, Hardware & Architecture; Computer Science, Theory &; Methods

Abstract

Network-on-chip (NoC) has been proposed to solve the scalability problem experienced in bus-based system-on-chip. The main challenge is the ability to predict the quality of service that the network infrastructure provides while meeting other system constraints, namely power and area. Although these architectures are regular with predictable electrical parameters, they may suffer from higher latency and lower throughput. To tackle this issue, the network structure needs to be adaptable in response to the needs of the application. This paper presents a methodology for augmenting an NoC with a programmable infrastructure that allows application-specific adaptation. Based on the developed infrastructure, an algorithm is also presented for static adaptation based on application traffic patterns. To evaluate the proposed methodology of the adaptable NoC, the WK-recursive on-chip interconnect is used as a case study. Simulations are conducted and reported results demonstrate the usefulness of the proposed approach.

Journal Title

Iet Computers and Digital Techniques

Volume

8

Issue/Number

3

Publication Date

1-1-2014

Document Type

Article

Language

English

First Page

109

Last Page

117

WOS Identifier

WOS:000337941800001

ISSN

1751-8601

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