Design and Analysis of an Area-Efficient High Holding Voltage ESD Protection Device

    Authors

    J. Zeng; S. R. Dong; J. J. Liou; Y. Han; L. Zhong;W. H. Wang

    Comments

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    Abbreviated Journal Title

    IEEE Trans. Electron Devices

    Keywords

    Area efficiency; double snapback phenomenon; floating p; gate-grounded; nMOS (GGnMOS) incorporated silicon-controlled rectifier (GGISCR); high; holding voltage; SILICON-CONTROLLED RECTIFIER; SCR; TRANSISTORS; OUTPUT; Engineering, Electrical & Electronic; Physics, Applied

    Abstract

    A novel electrostatic discharge protection device gate-grounded nMOS (GGnMOS) incorporated silicon-controlled rectifier (GGISCR) is proposed in this paper. With a distinguished feature of an imbedded floating P+ region, the GGISCR is demonstrated to be superior to the conventional low voltage triggered SCR and GGnMOS in terms of high area efficiency and high holding voltage. The operational mechanism of GGISCR device is discussed in detail, and the effect of floating P+ region on the GGISCR's I-V characteristics is analyzed via TCAD simulation results as well.

    Journal Title

    Ieee Transactions on Electron Devices

    Volume

    62

    Issue/Number

    2

    Publication Date

    1-1-2015

    Document Type

    Article

    Language

    English

    First Page

    606

    Last Page

    614

    WOS Identifier

    WOS:000348386100050

    ISSN

    0018-9383

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