Design and Analysis of an Area-Efficient High Holding Voltage ESD Protection Device
Abbreviated Journal Title
IEEE Trans. Electron Devices
Area efficiency; double snapback phenomenon; floating p; gate-grounded; nMOS (GGnMOS) incorporated silicon-controlled rectifier (GGISCR); high; holding voltage; SILICON-CONTROLLED RECTIFIER; SCR; TRANSISTORS; OUTPUT; Engineering, Electrical & Electronic; Physics, Applied
A novel electrostatic discharge protection device gate-grounded nMOS (GGnMOS) incorporated silicon-controlled rectifier (GGISCR) is proposed in this paper. With a distinguished feature of an imbedded floating P+ region, the GGISCR is demonstrated to be superior to the conventional low voltage triggered SCR and GGnMOS in terms of high area efficiency and high holding voltage. The operational mechanism of GGISCR device is discussed in detail, and the effect of floating P+ region on the GGISCR's I-V characteristics is analyzed via TCAD simulation results as well.
Ieee Transactions on Electron Devices
"Design and Analysis of an Area-Efficient High Holding Voltage ESD Protection Device" (2015). Faculty Bibliography 2010s. 6916.