Title

Analysis and enhancement of the LDMOSFET for safe operating area and device ruggedness

Abstract

ABSTRACT The Lateral Double-Diffused Metal-Oxide-Semiconductor Field Effect Transistor (LDMOSFET or LDMOS) has made an enormous impact in the field of power electronics. Its integration, low cost, and power performance have made it the popular choice for power system on chips (SoC's). Over the years, much research has gone into ways of optimizing this crucial power device. Particularly, the safe operating area (SOA) has become a focus of research in order to allow a wide range of various bias schemes. More so, device ruggedness is an important factor in the usability of these devices as there are many circuits in which high current and voltage are present in a device. In this study, a conventional LDMOS is simulated using a 2-D device simulator. Two specific device enhancement techniques are implemented and analyzed, including a p+ bottom layer and an n-adaptive layer. The parasitic BJT of the LDMOS and its effect on SOA is investigated by using meaningful and in depth device cross-section analysis. The ruggedness of these devices are then considered and analyzed by means of an undamped inductive switching test (UIS). The purpose is to realize the relationship and the possible trade-offs between safe operating area enhancement and device ruggedness.

Notes

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Thesis Completion

2010

Semester

Spring

Advisor

Yuan, Jiann S.

Degree

Bachelor of Science (B.S.)

College

College of Engineering and Computer Science

Degree Program

Electrical Engineering

Subjects

Dissertations, Academic -- Engineering and Computer Science;Engineering and Computer Science -- Dissertations, Academic

Format

Print

Identifier

DP0022734

Language

English

Access Status

Open Access

Length of Campus-only Access

None

Document Type

Honors in the Major Thesis

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