Abstract

Symmetrical/asymmetrical bidirectional S-shaped I-V characteristics with trigger voltages ranging from 10 V to over 40 V and relatively high holding current are obtained for advanced sub-micron silicided CMOS (Complementary Metal Oxide Semiconductor)/BiCMOS (Bipolar CMOS) technologies by custom implementation of P.sub.1-N.sub.2-P.sub.2-N.sub.1//N.sub.1-P.sub.3-N.sub.3-P.sub.1 lateral structures with embedded ballast resistance 58, 58A, 56, 56A and periphery guard-ring isolation 88-86. The bidirectional protection devices render a high level of electrostatic discharge (ESD) immunity for advanced CMOS/BiCMOS processes with no latchup problems. Novel design-adapted multifinger 354/interdigitated 336 layout schemes of the ESD protection cells allow for scaling-up the ESD performance of the protection structure and custom integration, while the I-V characteristics 480 are adjustable to the operating conditions of the integrated circuit (IC). The ESD protection cells are tested using the TLP (Transmission Line Pulse) technique,

Document Type

Patent

Patent Number

US 7,566,914 B2

Application Serial Number

11/289,390

Issue Date

7-28-2009

Current Assignee

Joint Assignment w/UCFRF: Intersil Corporation

Assignee at Issuance

Joint Assignment w/UCFRF: Intersil Corporation

College

College of Engineering and Computer Science (CECS)

Department

Electrical Engineering & Computer Science - CS Division

Allowance Date

3-20-2009

Filing Date

11-30-2005

Assignee at Filing

Joint Assignment w/UCFRF: Intersil Corporation

Filing Type

Nonprovisional Application Record

Donated

no

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