Abstract

A complementary SCR-based structure enables a tunable holding voltage for robust and versatile ESD protection. The structure are n-channel high-holding-voltage low-voltage-trigger silicon controller rectifier (N-HHLVTSCR) device and p-channel high-holding-voltage low-voltage-trigger silicon controller rectifier (P-HHLVTSCR) device. The regions of the N-HHLVTSCR and P-HHLVTSCR devices are formed during normal processing steps in a CMOS or BICMOS process. The spacing and dimensions of the doped regions of N-HHLVTSCR and P-HHLVTSCR devices are used to produce the desired characteristics. The tunable HHLVTSCRs makes possible the use of this protection circuit in a broad range of ESD applications including protecting integrated circuits where the I/O signal swing can be either within the range of the bias of the internal circuit or below/above the range of the bias of the internal circuit.

Document Type

Patent

Patent Number

US 7,202,114 B2

Application Serial Number

11/032,154

Issue Date

4-10-2007

Current Assignee

Joint Assignment w/UCFRF: Intersil Corporation

Assignee at Issuance

Joint Assignment w/UCFRF: Intersil Corporation

College

College of Engineering and Computer Science (CECS)

Department

Electrical Engineering & Computer Science - CS Division

Allowance Date

11-30-2006

Filing Date

1-11-2005

Assignee at Filing

Joint Assignment w/UCFRF: Intersil Corporation

Filing Type

Nonprovisional Application Record

Donated

no

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