Integrated circuits -- Design and construction, Metal oxide semiconductors, Complementary
Advancement in CMOS technology has become a driving force in the advancement of today's IC design arena. In the past few years, considerable research has been done on the CMOS devices and circuits. Constant efforts have been made to realize smaller and smaller devices by reducing the channel length of the transistors and scaling down various other device parameters. Consequently, various problems have arisen such as interconnect delay, signal integrity and signal coupling.
The purpose of this thesis is to review and understand current problems in IC design and come up with various solutions to them. Efforts have been made to propose a model of interconnect which demonstrates the effects of parasitic components on the chip. Signal coupling effects have been demonstrated by simulating various RC and RLC models for interconnects. The impact of parasitic inductance on the performance of the chip is understood with the help of simulation results.
The design of an eight bit shifter is realized using Clockless Asynchronous and Clocked Boolean design techniques. Both the chips are placed and routed using Silicon Ensemble, a high-tech CAD tool from Cadence Design Systems. Various optimization techniques have been applied to both the prototypes and a detailed comparison has been done considering factors such as area of the chip, total length of the interconnect, row utilization, chip congestion etc. Based on these results, it was found that Clocked Boolean Shifter was compact, compared to its Asynchronous counterpart design. However, Asynchronous Clockless architectures are well recommended where complex chip functionalities are intended to be integrated without much of the hassles of timing problems.
Yuan, Jiann S.
Master of Science (M.S.)
College of Engineering
Electrical Engineering and Computer Science
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Length of Campus-only Access
Masters Thesis (Open Access)
Orlando (Main) Campus
Dissertations, Academic -- Engineering; Engineering -- Dissertations, Academic
Sonchhatra, Jignesh Suresh, "Signal integrity in deep submicron CMOS chip design" (2000). Retrospective Theses and Dissertations. 1989.