Integrated circuit yield modeling : optimization and validation using wafer probe bin maps
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Liou, Juin J.
Master of Science (M.S.)
College of Engineering
Electrical and Computer Engineering
Length of Campus-only Access
Masters Thesis (Open Access)
Dissertations, Academic -- Engineering; Engineering -- Dissertations, Academic
Langford, Rick Edward, "Integrated circuit yield modeling : optimization and validation using wafer probe bin maps" (1998). Retrospective Theses and Dissertations. 2440.