A framework for validation and verification of simulation models in semiconductor manufacturing environment
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Master of Science (M.S.)
College of Engineering
Industrial Engineering and Management Systems
Length of Campus-only Access
Masters Thesis (Open Access)
Dissertations, Academic -- Engineering; Engineering -- Dissertations, Academic
Nayani, Nirupama, "A framework for validation and verification of simulation models in semiconductor manufacturing environment" (1997). Retrospective Theses and Dissertations. 2759.