This research report presents an introduction into phase lock loops (PLL) with a major emphasis on calculating phase noise in frequency synthesizers. A PLL model that incorporates the major sources of noise is presented for the purpose of design analysis. The model can be used to analyze second and fifth order PLLs which allows the accurate calculation of phase noise as a function of independent variable design parameters. The stability of PLLs is also analyzed to show the effects of a marginally stable system on the resultant phase noise. Developing an accurate PLL model which accounts for the major sources of noise and insures a stable closed loop system is the basis for calculating the phase noise of PLLs. Accurately specifying and then calculating the phase noise performance of PLLs, which are often used as local oscillators (LO) in receiver systems, is an important capability which insures the local oscillators are not the limiting factor in receiver system performance.
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Master of Science (M.S.)
College of Engineering
Electrical Engineering and Communication Sciences
Length of Campus-only Access
Masters Thesis (Open Access)
Dissertations, Academic -- Engineering; Engineering -- Dissertations, Academic
Pavik, Diane Marie, "Analysis of Phase Noise in Phase Lock Loop" (1988). Retrospective Theses and Dissertations. 4325.