Title

Scale-Space Chip

Abstract

A single-chip VLSI design is proposed for scale-space computation in one and two dimensions. The architecture of the chip is based on an algorithm that can provide speeds that are an order of magnitude higher than the speeds obtainable from the other systems proposed in the literature. The design uses the principles of modularity, expandability, and parallelism and fully utilizes the three properties of the Gaussian: symmetry, separability, and scaling. The proposed algorithm and the hardware architecture use a very high degree of pipelining and parallelism. The chip can be implemented in either nMOS or CMOS technology.

Publication Date

12-1-1988

Publication Title

Proceedings - International Conference on Pattern Recognition

Number of Pages

420-424

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

Socpus ID

0024172296 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/0024172296

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