Title

Multibit Decoding/Encoding Of Binary Codes Using Memory Based Architectures

Abstract

We present new memory based architectures for the design of special purpose hardware for real-time compression and decompression of data. The architecture is based on a novel idea of mapping the decode/encode tree of any binary code on to a memory device that corresponds to simultaneous decoding/encoding of multiple bits. The hardware is programmable, adaptable and yields a high compression rate. Using 1 μm CMOS process technology, this could easily lead to over 100 Mbits/sec compression rate for the JPEG baseline compression scheme.

Publication Date

1-1-1991

Publication Title

Data Compression Conference Proceedings

Volume

1991-April

Number of Pages

352-361

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/DCC.1991.213345

Socpus ID

84982446030 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/84982446030

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