Title

A Unified Four-Terminal Jfet Static Model For Circuit Simulation

Abstract

Junction field-effect transistors (JFETs) are useful for signal mixing purposes because of the isolated top- and bottom-gate terminals in such devices. Difficulties often arise, however, when one simulates the operation of a four-terminal JFET because the conventional JFET model treats the top and bottom gates as a single terminal. In this paper, we develop a unified four-terminal JFET static model covering both linear and saturation regions and including important device physics such as subthreshold behavior and asymmetrical top- and bottom-gate depletion layer thicknesses. Experimental data measured from JFETs fabricated at Harris Semiconductor is included in support of the model. © 1991.

Publication Date

1-1-1991

Publication Title

Solid State Electronics

Volume

34

Issue

5

Number of Pages

437-443

Document Type

Article

Personal Identifier

scopus

DOI Link

https://doi.org/10.1016/0038-1101(91)90147-Q

Socpus ID

0026152173 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/0026152173

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