Title

A parallel butterfly algorithm and VLSI architectures for image decorrelation

Abstract

We present a new high speed parallel architecture and its VLSI implementation to design a special purpose hardware for real-time lossless image compression/decompression using a decorrelation scheme. The proposed architecture can easily be implemented using state-of-the-art VLSI technology. The hardware yields a high compression rate. A prototype 1-micron VLSI chip based on this architectural idea has been designed. The scheme is favourably comparable to the JPEG baseline loseless image compression schemes. We also discuss the parallelization issues of the JPEG baseline standard still compression schemes and their difficulties.

Publication Date

5-2-1994

Publication Title

Proceedings of SPIE - The International Society for Optical Engineering

Volume

2187

Number of Pages

322-332

Document Type

Article; Proceedings Paper

Identifier

scopus

Personal Identifier

scopus

DOI Link

https://doi.org/10.1117/12.174967

Socpus ID

85076643496 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/85076643496

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