Title

SAS: a yield/failure analysis software tool

Abstract

As the device sizes decrease and the number of interconnect levels and wafer size increase, the device yield and failure analysis becomes more complex. Currently, software tools are being used to perform visual inspection techniques after many operations during which defects are detected on a sample of wafers. However, it has been observed that the correlation between the yield predicted on the basis of the defects found during such observations and the yield determined electrically at wafer final test is low. Of a greater interest to yield/failure analysis software tools is statistical analysis software. SAS TM can perform extensive data analysis on kerf test structures' electrical parameters. In addition, the software can merge parametric and yield/fail bins data which reduces the data collection and data reduction activities involved in the correlation of device parameters to circuit functional operation. The data is saved in large databases which allow storage and later retrieval of historical data in order to evaluate process shifts and changes and their effect on yield. The merge of process parameters and on-line measurements with final electrical data, is also possible with the aid of process parameter extraction software. All of this data analysis provides excellent feedback about integrated circuit wafer processing.

Publication Date

12-1-1996

Publication Title

Proceedings of SPIE - The International Society for Optical Engineering

Volume

2874

Number of Pages

210-218

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

Socpus ID

0030411902 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/0030411902

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