Title

Circuit analysis of BiCMOS gate delay

Abstract

A circuit analysis of the BiCMOS switching transient is presented. The BiCMOS pull-up delay as a function of transistor parameters and power supply voltage is evaluated. The analytical predictions are compared with SPICE circuit simulation. Good agreement between the model and SPICE simulation is obtained. Twodimensional numerical device simulation is used to examinethe physical insight into BiCMOS device operation. © 1997 Taylor and Francis Group, LLC.

Publication Date

1-1-1997

Publication Title

International Journal of Electronics

Volume

83

Issue

1

Number of Pages

1-12

Document Type

Article

Personal Identifier

scopus

DOI Link

https://doi.org/10.1080/002072197135580

Socpus ID

21544442595 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/21544442595

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