Title

Designing High-Performance Processors Using Real Address Prediction

Keywords

Address prediction; address translation; cache; pipelined; processor; synonym

Abstract

In this correspondence, we propose design techniques that may significantly simplify the cache access path, and hence offer the opportunity of shorter cycle time or fewer pipeline stages. Our proposals are based on highly accurate prediction methods that allow us to efficiently resolve address translation information early in the pipe. © 1993 IEEE

Publication Date

1-1-1993

Publication Title

IEEE Transactions on Computers

Volume

42

Issue

9

Number of Pages

1146-1151

Document Type

Article

Identifier

scopus

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/12.241604

Socpus ID

0027658596 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/0027658596

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