Title
A 5Ghz Fully Integrated Super-Regenerative Receiver With On-Chip Slot Antenna In 0.13Μm Cmos
Abstract
A single chip receiver based on super-regeneration incorporates an on-chip slot antenna and digital received data synchronization. A capacitively-loaded standing-wave resonator improves energy efficiency. An all-digital PLL timing scheme synchronizes the received data clock. The prototype 5GHz receiver, implemented in 0.13μm CMOS, achieves a data rate of up to 1.2Mb/s, dissipates 6.6mW from a 1.5V supply, and occupies a die area of 2.4mm2. © 2008 IEEE.
Publication Date
9-23-2008
Publication Title
IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Number of Pages
34-35
Document Type
Article; Proceedings Paper
Personal Identifier
scopus
DOI Link
https://doi.org/10.1109/VLSIC.2008.4585941
Copyright Status
Unknown
Socpus ID
51949105602 (Scopus)
Source API URL
https://api.elsevier.com/content/abstract/scopus_id/51949105602
STARS Citation
Shi, Dan; Behdad, Nader; Chen, Jia Yi; and Flynn, Michael P., "A 5Ghz Fully Integrated Super-Regenerative Receiver With On-Chip Slot Antenna In 0.13Μm Cmos" (2008). Scopus Export 2000s. 10210.
https://stars.library.ucf.edu/scopus2000/10210