Title

Window-Masked Segmented Digital Clock Manager-Fpga-Based Digital Pulsewidth Modulator Technique

Keywords

DC-DC converters; Digital control; Digital power electronics; Digital pulsewidth modulators (DPWM); Field programmable gate arrays

Abstract

This paper presents a new digital pulsewidth modulator (DPWM) architecture for field programmable gate array (FPGA)-based systems. The design of the proposed DPWM architecture is based on fully utilizing the digital clock manager (DCM) resources available on new FPGA boards. Furthermore, this architecture will also window-mask the DCM operationtoonly a portion of the switching period in order to decrease power dissipation. This proposed digital modulator technique allows for higher DPWM resolution with lower power consumption, the primary barrier to high switching frequency operation. The presented technique relies on power-optimized resources already existing on new FPGAs, and benefits from the inherit phase-shifting properties of the DCM blocks, which help in simplifying the duty cycle generation. The architecture can be applied to achieve different numbers of bits for the DPWM resolution designed for different dc-dc applications. The suggested architecture is first simulated, implemented, and experimentally verified on a Virtex-4 FPGA board. © 2009 IEEE.

Publication Date

12-1-2009

Publication Title

IEEE Transactions on Power Electronics

Volume

24

Issue

11

Number of Pages

2649-2660

Document Type

Article

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/TPEL.2009.2033066

Socpus ID

77952113729 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/77952113729

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