Title

Efficient Vlsi Architecture For Video Transcoding

Keywords

DCT and IDCT; Motion estimation and compensation; Unified architecture; Video transcoding

Abstract

In this paper, we present a unified architecture that can perform Discrete Cosine Transform (DCT), Inverse Discrete Cosine Transform (IDCT), DCT domain motion estimation and compensation (DCT-ME/MC). Our proposed architecture is a Wavefront Array-based Processor with a highly modular structure consisting of 8 × 8 Processing Elements (PEs). By utilizing statistical properties and arithmetic operations, it can be used as a high performance hardware accelerator for video transcoding applications. We show how different core algorithms can be mapped onto the same hardware fabric and can be executed through the pre-defined PEs. In addition to the simplified design process of the proposed architecture and savings of the hardware resources, we also demonstrate that high throughput rate can be achieved for IDCT and DCT-MC by fully utilizing the sparseness property of DCT coefficient matrix. © 2009 IEEE.

Publication Date

10-29-2009

Publication Title

IEEE Transactions on Consumer Electronics

Volume

55

Issue

3

Number of Pages

1462-1470

Document Type

Article

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/TCE.2009.5278014

Socpus ID

70350263667 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/70350263667

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