Title

Electrostatic Discharge Robustness Of Si Nanowire Field-Effect Transistors

Keywords

Electrostatic discharge (ESD); Failure current I t2; Nanowire (NW) field-effect transistor; ON-state resistance

Abstract

Electrostatic discharge (ESD) performance of N-type double-gated Si nanowire (NW) thin-film transistors is investigated, for the first time, using the transmission line pulsing technique. The ESD robustness of these devices depends on the NW dimension, number of channels, plasma treatment, and layout topology. The failure currents, leakage currents, and on-state resistances are characterized, and possible ESD protection applications of these devices for future NW field-effect-transistor-based integrated circuits are also discussed. © 2009 IEEE.

Publication Date

7-24-2009

Publication Title

IEEE Electron Device Letters

Volume

30

Issue

9

Number of Pages

969-971

Document Type

Article

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/LED.2009.2025610

Socpus ID

69949160152 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/69949160152

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