Title

Delay-Insensitive Gate-Level Pipelining

Keywords

Asynchronous logic design; Dual-rail encoding; NULL convention logic (NCL); Pipelining; Self-timed circuits

Abstract

Gate-level pipelining (GLP) techniques are developed to design throughput-optimal delay-insensitive digital systems using NULL convention logic (NCL). Pipelined NCL systems consists of combinational, registration, and completion circuits implemented using threshold gates equipped with hysteresis behavior. NCL combinational circuits provide the desired processing behavior between asynchronous registers that regulate wavefront propagation. NCL completion logic detects completed DATA or NULL output sets from each register stage. GLP techniques cascade registration and completion elements to systematically partition a combinational circuit and allow controlled overlapping of input wavefronts. Both full-word and bit-wise completion strategies are applied progressively to select the optimal size grouping of operand and output data bits. To illustrate the methodology, GLP is applied to a case study of a 4-bit×4-bit unsigned multiplier, yielding a speedup of 2.25 over the non-pipelined version, while maintaining delay insensitivity. © 2001 Elsevier Science B.V. All rights reserved.

Publication Date

10-1-2001

Publication Title

Integration, the VLSI Journal

Volume

30

Issue

2

Number of Pages

103-131

Document Type

Article

Personal Identifier

scopus

DOI Link

https://doi.org/10.1016/S0167-9260(01)00013-X

Socpus ID

0035475076 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/0035475076

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