Title

Routing On Field-Programmable Switch Matrices

Keywords

Field programmable gate arrays (FPGAs); Interconnect structures; Multi-FPGA systems; Switch routing

Abstract

In this paper, we address the problem of routing nets on field programmable gate arrays (FPGAs) interconnected by a switch matrix. We extend the switch matrix architecture proposed by Zhu et al. to route nets between FPGA chips in a multi-FPGA system. Given a limited number of routing resources in the form of programmable connection points within a two-dimensional switch matrix, this problem examines the issue of how to route a given net traffic through the switch matrix structure. First, we define the problem as a general undirected graph in which each vertex has one single color among six possible colors and formulate it as a constraint satisfaction problem. This is further modeled as a 0-1 multidimensional knapsack problem for which a fast approximate solution is applied. Experimental results show that the accuracy of our proposed heuristic is quite high for moderately large switch matrices.

Publication Date

4-1-2003

Publication Title

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volume

11

Issue

2

Number of Pages

283-287

Document Type

Article

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/TVLSI.2003.810778

Socpus ID

0042769403 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/0042769403

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