Title

High Throughput Power-Aware Fir Filter Design Based On Fine-Grain Pipelining Multipliers And Adders

Keywords

Added delay; Clocks; Computer science; Digital signal processing; Finite impulse response filter; Mobile communication; Pipeline processing; Power dissipation; Throughput; Timing

Abstract

In regular FIR structure, by pipelining the multipliers one can improve the throughput. But as with the growth of operand word length, the delay in addition process becomes another important constraint. In this paper, a novel fine-grain pipelining scheme for high throughput FIR is proposed. By pipelining multipliers and adders, very high throughput can be achieved. 2-dimensional pipeline gating technique is used to make the designed FIR power aware of the precision of the operands. The average power dissipation and latency are both significantly reduced with changing of input precisions.

Publication Date

1-1-2003

Publication Title

Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI

Volume

2003-January

Number of Pages

260-261

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/ISVLSI.2003.1183490

Socpus ID

84942025467 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/84942025467

This document is currently not available here.

Share

COinS