Title

An Adaptive Supply-Voltage Scheme For Low Power Self-Timed Cmos Digital Design

Keywords

Capacitance; Circuit simulation; Clocks; Communication system control; Delay; Dynamic voltage scaling; Logic circuits; Power dissipation; Signal detection; Timing

Abstract

This paper combines an adaptive supply-voltage scheme with self-timed CMOS digital design, to achieve low power performance. The supply-voltage automatically tracks the input data rate of the data path so that the supply-voltage can be kept as small as possible while maintaining the speed requirement. This adaptive supply-voltage scheme employs the handshake signals directly to detect the speed of data path without using FIFO buffer. This leads to a very simple logic control whose power loss is negligible. Cadence SPICE simulation shows the effectiveness of this scheme for low power applications based on 0.18 μm CMOS process.

Publication Date

1-1-2003

Publication Title

Proceedings of the IEEE International Conference on VLSI Design

Volume

2003-January

Number of Pages

315-319

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/ICVD.2003.1183156

Socpus ID

84856950219 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/84856950219

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