Title

Srsl Pipelining Of Coarse-Grain Datapaths

Abstract

In this paper, we propose a clockless handshake mechanism based on self-resetting stage logic targeted for pipelined datapaths. In this logic, a stage resets itself after it completes the evaluation of its embedded logic. As such, a stage oscillates between a reset phase and an evaluate phase thus completing a single period. This handshake mechanism is incorporated into two distinct pipelines where its coordination is limited to each pair of neighboring stages in the first pipeline, while it is driven by the last stage in the second pipeline. Implementation results of both pipelines show that they can reach throughputs of several hundred Mega outputs per second, while they can easily reach the 1.4 Giga outputs per second if implemented as FIFOs.

Publication Date

12-1-2005

Publication Title

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Number of Pages

-

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/ICECS.2005.4633511

Socpus ID

56749177818 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/56749177818

This document is currently not available here.

Share

COinS