Title

Energy-Aware Dual-Rail Bit-Wise Completion Pipelined Multipliers Design

Abstract

Energy-awareness indicates the scalability of the system energy with changing conditions and quality requirements. Because of the encoding format and operation sequence, dual-rail encoding circuits do not naturally energy aware to the changing of input precision. A novel technique, Zero Insertion, to design energy-aware arithmetic circuits in dual-rail encoding logic is developed. By using Null's to replace the redundant Data 0's in high order bits, the designed circuits have significant energy savings as well as latency reduction under different input precision probability while maintaining speed-independency. A group of parallel multipliers have been designed and simulated to demonstrate the effectiveness of this technique. The overhead and additional costs in control signal generation circuit are also discussed. © 2005 IEEE.

Publication Date

11-9-2005

Publication Title

Conference Proceedings - IEEE SOUTHEASTCON

Number of Pages

49-54

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

Socpus ID

27544476094 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/27544476094

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