Title

Simulation Framework For Multi-Processor Memory Communications

Abstract

In this paper, we propose a packet-based, off-chip, multi-processor/memory simulation framework to measure the performance of interconnect architectures linking network processors and memories on line cards. The simulator architecture utilizes software methodologies, such as STL, pure virtual functions, and singleton classes, which provide a great deal of modularity in constructing the physical and functional system modules and allow future scalability. The simulator includes performance enhancing features to route, switch, and control packet flows in order to minimize congestion spots within the interconnects and packet loss. Packets are routed adaptively among processors and memories following a non-uniform traffic patterns. The simulator provides multiple comprehensive reports that include detailed information about generated messages, traffic load, and performance metrics. The goal of utilizing the proposed simulator is to find which interconnect topology and configuration can provide the highest memory bandwidth that exceeds the existing shared-bus system currently being deployed on line cards. Performance results show that κ-ary n-cube interconnects, using our routing algorithm and enhancement features, can sustain current line rates and higher, while distributing the load among multiple memories.

Publication Date

1-1-2005

Publication Title

2005 European Simulation and Modelling Conference, ESM 2005 - Proceedings

Number of Pages

413-419

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

Socpus ID

84898413901 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/84898413901

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