Title
On The Design Of Tunable High-Holding-Voltage Lvtscr-Based Cells For On-Chip Esd Protection
Abstract
Optimization of the lateral dimensions of an LVTSCR-based ESD cell allows flexible tuning of the I-V characteristics and maximization of the cells' performance under snapback conditions during the high current regime of an ESD event. Once the trigger point is reached and the voltage snaps back, the holding voltage is dependent on lateral arrangement of the wells' implantations and changes in the cell's interconnections. Appropriate choices of these dimensions and interconnections permit design of tunable high holding voltages over a wide range. This paper presents the design optimization method and I-V characteristics of cells fabricated for different operational conditions and ultimate on-chip ESD protection schemes extendable to a variety of technologies. © 2004 IEEE.
Publication Date
12-1-2004
Publication Title
International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT
Volume
2
Number of Pages
798-803
Document Type
Article; Proceedings Paper
Personal Identifier
scopus
Copyright Status
Unknown
Socpus ID
21644444756 (Scopus)
Source API URL
https://api.elsevier.com/content/abstract/scopus_id/21644444756
STARS Citation
Salcedo, J. A.; Liou, J. J.; and Bernier, J. C., "On The Design Of Tunable High-Holding-Voltage Lvtscr-Based Cells For On-Chip Esd Protection" (2004). Scopus Export 2000s. 4850.
https://stars.library.ucf.edu/scopus2000/4850