Title

A 3D Bus Interconnect For Network Line Cards

Abstract

In this paper, we propose a 3D bus architecture as a processor-memory interconnection system to increase the throughput of the memory system currently used on line cards. The 3D bus architecture allows multiple processing elements on a line card to access a shared memory. The main advantage of the proposed architecture is to increase the network processor off-chip memory bandwidth while diminishing the latency otherwise caused by the single bus competition. ©2004 IEEE.

Publication Date

12-1-2004

Publication Title

Conference Proceedings - 2nd Annual IEEE Northeast Workshop on Circuits and Systems, NEWCAS 2004

Number of Pages

257-260

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

Socpus ID

14844314885 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/14844314885

This document is currently not available here.

Share

COinS