Title

Pipeline-Level Control Of Self-Resetting Pipelines

Abstract

In this paper, we present a novel synchronization approach to support data flow in clockless designs using single-rail encoding. This approach is based on self-resetting stage logic in which a pipeline stage resets itself before starting the next execution cycle. As such, a stage goes through a reset phase when its output is null, and an evaluate phase when its output is the result of the evaluation of its inputs. To insure correct operation, data flow from one stage to another when the preceding stage is in the evaluate phase while the following stage is in the reset phase. To support this data flow, a latch-based synchronization mechanism is proposed. This mechanism yields an efficient and simple uni-directional handshaking scheme emanating from the last stage in the pipeline back towards the remaining stages of the pipeline. This handshaking scheme is extended to handle the join and forks of data flows encountered in non-linear pipelines. A concept design of a four-bit 16-stage pipeline is presented to illustrate the inner workings of self-resetting stage logic and its data-flow synchronization mechanism. The signal timing analysis of this pipeline reveals that the duration of the evaluate and reset phase remains constant in the stages located to the left of the last stage in the pipeline. As a result, the last stage operates as a pulse generator with which the remaining stages of the pipeline synchronize in such a way that neighboring stages operates in opposing phases at each cycle of execution.

Publication Date

12-1-2004

Publication Title

Proceedings of the EUROMICRO Systems on Digital System Design, DSD 2004

Number of Pages

342-349

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/DSD.2004.1333295

Socpus ID

13944281762 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/13944281762

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