Title

Smtp: An Architecture For Next-Generation Scalable Multi-Threading

Abstract

We introduce the SMTp architecture - an SMT processor augmented with a coherence protocol thread context, that together with a standard integrated memory controller can enable the design of (among other possibilities) scalable cache-coherent hardware distributed shared memory (DSM) machines from commodity nodes. We describe the minor changes needed to a conventional out-of-order multi-threaded core to realize SMTp, discussing issues related to both deadlock avoidance and performance. We then compare SMTp performance to that of various conventional DSM machines with normal SMT processors both with and without integrated memory controllers. On configurations from 1 to 32 nodes, with 1 to 4 application threads per node, we find that SMTp delivers performance comparable to, and sometimes better than, machines with more complex integrated DSM-specific memory controllers. Our results also show that the protocol thread has extremely low pipeline overhead. Given the simplicity and the flexibility of the SMTp mechanism, we argue that next-generation multi-threaded processors with integrated memory controllers should adopt this mechanism as a way of building less complex high-performance DSM multiprocessors.

Publication Date

10-8-2004

Publication Title

Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA

Volume

31

Number of Pages

124-135

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

Socpus ID

4644289581 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/4644289581

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