Title

Control And Data Flow Graph Extraction For High-Level Synthesis

Abstract

The first step in high level synthesis consists of translating a behavioral specification into its corresponding Register Transfer Language (RTL) description. Behavioral specifications are composed by writing code in a hardware description language such as VHDL. The process of translation starts by first deriving a control and data flow graph (CDFG) from the source code of the behavioral specification. The derivation of the CDFG has been mostly done manually, which makes this process time-consuming and error-prone at least in the earlier stages of synthesis. In this paper, we describe a tool that we have developed for automatic conversion of the given VHDL behavioral specification of a circuit into its corresponding CDFG. Since there is no widely accepted format for representing CDFGs, we opted to make the tool generate several representations of the derived CDFG in different formats to accommodate different implementation approaches. This design decision makes our tool quite flexible and highly useful. The proposed tool has been tested on operation and control-dominated behavioral specifications to insure its accuracy. Experimental results on benchmark circuits show that the tool is highly accurate and can produce a CDFG in a few seconds using minimal computing resources.

Publication Date

9-24-2004

Publication Title

Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design

Number of Pages

187-192

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/ISVLSI.2004.1339528

Socpus ID

4544258165 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/4544258165

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