Title

Energy-Efficient Self-Timed Circuit Design Using Supply Voltage Scaling

Abstract

Energy-efficient design for self-timed circuits is investigated. Null convention logic is employed to construct speed-independent self-timed circuits. For error-free computation, the supply voltage automatically tracks the input data rate so that the supply voltage can be kept as small as possible while maintaining the speed requirement. For error-tolerable computation, such as soft digital signal processing, further energy saving is achieved at the cost of signal-to-noise ratio when an ultralow supply voltage is applied. Cadence simulation shows that 40 to 70% power can be saved by introducing -15 to -11 dB error in typical speech signal processing. © IEE, 2004.

Publication Date

8-1-2004

Publication Title

IEE Proceedings: Circuits, Devices and Systems

Volume

151

Issue

4

Number of Pages

278-284

Document Type

Article

Personal Identifier

scopus

DOI Link

https://doi.org/10.1049/ip-cds:20040296

Socpus ID

5044251131 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/5044251131

This document is currently not available here.

Share

COinS