Title

Prototyping Of Efficient Hardware Algorithms For Data Compression In Future Communication Systems

Abstract

Due to high bandwidth requirements up to 2 Mbits/sec in third generation mobile communication systems, efficient data compression approaches are necessary to reduce communication and storage costs. Recent VLSI technologies status promises complete System-on-Chip (SoC) solutions for both mobile and network based communication systems, including new compression algorithms based on Burrows-Wheeler transform (BWT). The most complex task of the BWT algorithm is its lexicographic sorting of n cyclic rotations or a given string of n characters. The paper discusses the feasibility and VLSI implementation of this scalable BWT architecture in simulating and prototyping its systolic highly utilized hardware structure with Virtex FPGAs.

Publication Date

1-1-2001

Publication Title

Proceedings of the International Workshop on Rapid System Prototyping

Number of Pages

58-63

Document Type

Article

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/IWRSP.2001.933839

Socpus ID

0034847143 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/0034847143

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