Title

Optimizing Dual-Core Execution For Power Efficiency And Transient-Fault Recovery

Keywords

Fault tolerance; Low-power design; Multiple data stream architectures

Abstract

Dual-core execution (DCE) is an execution paradigm proposed to utilize chip multiprocessors to improve the performance of single-threaded applications. Previous research has shown that DCE provides a complexity-effective approach to building a highly scalable instruction window and achieves significant latency-hiding capabilities. In this paper, we propose to optimize DCE for power efficiency and/or transient-fault recovery. In DCE, a program is first processed (speculatively) in the front processor and then reexecuted by the back processor. Such reexecution is the key to eliminating the centralized structures that are normally associated with very large instruction windows. In this paper, we exploit the computational redundancy in DCE to improve its reliability and its power efficiency. The main contributions include: 1) DCE-based redundancy checking for transient-fault tolerance and a complexity-effective approach to achieving full redundancy coverage and 2) novel techniques to improve the power/energy efficiency of DCE-based execution paradigms. Our experimental results demonstrate that, with the proposed simple techniques, the optimized DCE can effectively achieve transient-fault tolerance or significant performance enhancement in a power/ energy-efficient way. Compared to the original DCE, the optimized DCE has similar speedups (34 percent on average) over single-core processors while reducing the energy overhead from 93 percent to 31 percent. © 2007 IEEE.

Publication Date

8-1-2007

Publication Title

IEEE Transactions on Parallel and Distributed Systems

Volume

18

Issue

8

Number of Pages

1080-1093

Document Type

Article

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/TPDS.2007.4288106

Socpus ID

34548234204 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/34548234204

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