Title

Self-Timed Architecture For Masked Successive Approximation Analog-To-Digital Conversion

Keywords

Analog-to-digital conversion; Asynchronous digital systems; Null convention logic; Self-timed designs; Successive approximation

Abstract

In this paper, a novel architecture for self-timed analog-to-digital conversion is presented and designed using the NULL Convention Logic (NCL) paradigm. This analog-to-digital converter (ADC) employs successive approximation and a one-hot encoded masking technique to digitize analog signals. The architecture scales readily to any given resolution by utilizing the one-hot encoded scheme to permit identical logical components for each bit of resolution. The four-bit configuration of the proposed design has been implemented and assessed via simulation in 0.18-μm CMOS technology. Furthermore, the ADC may be interfaced with either synchronous or four-phase asynchronous digital systems. © World Scientific Publishing Company.

Publication Date

2-1-2007

Publication Title

Journal of Circuits, Systems and Computers

Volume

16

Issue

1

Number of Pages

1-14

Document Type

Article

Personal Identifier

scopus

DOI Link

https://doi.org/10.1142/S0218126607003551

Socpus ID

34249301757 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/34249301757

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