Title

A Review Of Core Compact Models For Undoped Double-Gate Soi Mosfets

Keywords

Asymmetric double-gate (DG) MOSFET; Drain-current model; Intrinsic channel; MOS compact modeling; Multigate MOSFET; Silicon-on-insulator (SOI) MOSFET; Symmetric DG MOSFET; Undoped body MOS

Abstract

In this paper, we review the compact-modeling framework for undoped double-gate (DG) silicon-on-insulator (SOI) MOSFETs. The use of multiple gates has emerged as a new technology to possibly replace the conventional planar MOSFET when its feature size is scaled to the sub-50-nm regime. MOSFET technology has been the choice for mainstream digital circuits for very large scale integration as well as for other high-frequency applications in the low-gigahertz range. But the continuing scaling of MOSFET presents many challenges, and multiple-gate, particularly DG, SOI devices seem to be attractive alternatives as they can effectively reduce the short-channel effects and yield higher current drive. Core compact models, including the analysis for surface potential and drain-current, for both the symmetric and asymmetric DG SOI MOSFETs, are discussed and compared. Numerical simulations are also included in order to assess the validity of the models reviewed. © 2007 IEEE.

Publication Date

1-1-2007

Publication Title

IEEE Transactions on Electron Devices

Volume

54

Issue

1

Number of Pages

131-140

Document Type

Review

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/TED.2006.887046

Socpus ID

33846059690 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/33846059690

This document is currently not available here.

Share

COinS